Class-D amplifiers are very much used in modern devices because of their high efficiency. A general class D output stage comprises a high-side switch MH and a low-side switch ML, as shown in FIG. 1a. Output signal will be pulses having a maximum value equaling the positive supply voltage Vdd and a minimum value equaling the negative one i.e. Vss. In general, the maximum supply voltage of the output stage equals the maximum process voltage and often the gate breakdown voltage dictates it. The source to drain voltage can handle a larger voltage. When the supply voltage has to be larger than this maximum process voltage a cascoded output stage may be used as shown in FIG. 1b. Two cascoded transistors have been added i.e. MLC, MHC, which will distribute the supply voltage over two MOS transistors. When the output voltage equals the positive supply voltage Vdd the voltage is divided over MLS and MLC. When the output voltage equals the negative supply voltage Vss the voltage is divided over MHS and MHC. Several solutions for the single transistor solution, FIG. 1a, are already known. The transistors should be driven in such a way that there is no cross current; short circuits between the supply voltages Vdd-Vss due to the fact that both high-side and low-side transistors are switched on. Currently, three solutions may be used for solving this problem:    1. Add a delay time between the high-side drive signal Input high in FIG. 1a and the low-side drive signal Input low. Now, first the low-side power transistor ML will be turned off; then wait to be sure that it is off; then turn on the high-side transistor (MH), and vice versa.    2. Using handshake signals Detection circuits at the power transistors (ML end MH) generates signals that indicate when these transistors are switched on or off. This signal will be used to drive the opposite transistor.    3. Using zero dead time as shown in US-A-2005/0218988.
Solutions one and two have a disadvantage that they will add dead time to the system; a moment that both power transistors ML and MH are switched off. This will result in worse performance e.g. in audio amplifiers an increase of THD.
Using cascoded output stages like in FIG. 1b, the flank of the output signal is not controlled in one of the above-mentioned solutions, which will end up in an increase of higher harmonic signals resulting in EMI problems. Furthermore, the reference voltages VtabL and VtabH have to handle large spike currents during output transitions.
Current solutions have some drawbacks; due to the uncontrolled output slope one has to deal with large distortions and EMI problems. Also, the charge and discharge of the cascoded transistors will be very fast resulting in large current spikes at the gate of the cascoded transistors. The cascoded transistors are connected to an internal bias voltage source. In order to not lift up these bias voltages too much, the output impedance of this bias voltage source has to be low. It will cost supply current.
FIG. 2 shows the simulation results of the current driver technique of the solution presented in US-A-2005/0218988.
First, consider a single power output stage like having a switching with zero dead time as described in US-A-2005/0218988A1. Inverters Mdlr/Mdls and Mdhr/Mdhs drive the power transistors shown in FIG. 3, ML and MH. To guarantee no cross currents with zero dead time the dimension of the inverters are critical. Several operating areas can be determined during the switching of the output. For this example no load has been connected to the output. Starting with the drive voltage Vdrive high and therefore the output voltage high Vout is about Vdd. Switching the output low i.e. Vout equals Vss, the drive voltage Vdrive will be set low at t0. The total gate capacitor Cgsh of the high side power transistor MH has to be discharged while the total gate capacitor Cgsl from the low side power transistor ML has to be charged in the same time. The discharge of the high side parasitic capacitor Cgsh will be with a voltage range from the maximum voltage to the threshold voltage of the high side power transistor MH. The charge of the low side capacitor Cgsl will be from Vss to the threshold voltage of the low side transistor ML. This will determine the ratio of the driver components Mdhr and Mdls of high side discharge and low side charge. Now, the high side transistor MH is just turned off and the low side turned ML on, the output voltage Vout can be switched to Vss. This is done by the current of the charge driver of the low side transistor Id,Mdls and the gate drain capacitor Cdgl of the low side transistor (ML), a linear output transition occur
      (                            ⅆ          Vout                          ⅆ          t                    =              I        C              )    .The gate voltage of the low side transistor ML will stay at the threshold voltage VTL.
Finally, the gate voltage of the low side will rise till it's maximum voltage Vdd resulting in a minimum on-resistance of the power transistor ML. Switching the output voltage Vout from Vss to Vdd will follow the same procedure. When the current of the drivers are independent of the supply voltage, the output transition dV/dt will be independent of the supply voltage.